An analog input signal can be converted into a digital output word using an analog-to-digital converter (ADC), which contains a mixture of analog and digital circuitry. The speed, resolution and linearity of the conversion affects the accuracy with which the digital output word represents the analog input signal. The conversion speed must be high enough to sample the shortest analog input signal period (highest analog signal frequency) at least twice. The conversion resolution is determined by the number of bits in the digital output word and has to be large enough to resolve the maximum peak-to-peak analog input signal into a required degree of granularity. The conversion linearity has to be sufficient to operate at or preferably below a required maximum level of distortion associated with the conversion process.
Several different algorithms and architectures exist that may be employed to accomplish a conversion. These include sigma delta, successive approximation, pipeline and flash ADCs in increasing order of bandwidth capability. Of particular interest is the sigma delta ADC, which typically provides a reasonable trade-off between sampling rate and bits of resolution while providing a low component count that benefits cost of production, size and reliability.
The sigma delta ADC employs sigma delta modulation techniques that digitize an input signal using very low resolution (one-bit) and a very high sampling rate (often in the megahertz range). Oversampling and the use of digital filters increases the resolution to as many as twenty or more bits. It is especially useful for high resolution conversion of low to moderate frequency signals as well as low distortion conversion of signals containing audio frequencies due to its inherent qualities of good linearity and high accuracy.
In its basic form, the sigma delta ADC employs an input modulator and an output digital filter and decimator. The input modulator operates by accepting an input signal through an input summing junction, which feeds a loop filter. The loop filter basically provides an integrated value of this signal to a comparator, which acts as a one-bit quantizer. The comparator output signal is fed back to the input summing junction through a circuit acting as a one-bit digital to analog converter. The feedback loop forces the average of the feedback signal to be substantially equal to the input signal. The density of “ones” in the comparator output signal is proportional to the value of the input signal. The input modulator oversamples the input signal by clocking the comparator at a rate that is much higher than the Nyquist rate. Then, the output digital filter and decimator produce output data words at a data rate appropriate to the conversion.
Quantization noise (or quantization error) is one of the factors that limits the dynamic range of an ADC. When an analog input signal is quantized, the quantization error is actually the “round off” error that occurs and has a magnitude that is typically one-half the value represented by the conversions least significant bit. The quantization error is usually random and therefore may be treated as white noise. An input signal sampled at the Nyquist rate has its associated quantization noise folded into the input signal bandwidth.
Oversampling the input signal causes the quantization noise to be spread over a wider bandwidth thereby reducing the level of quantization noise in the signal bandwidth by the oversampling ratio (oversampling rate/Nyquist rate). Additionally, the oversampled modulator also redistributes energy from the signal bandwidth to higher frequencies thereby providing further advantageous noise shaping.
General purpose sigma delta ADCs are often designed to be employed in a spectrum of applications having differing input signal bandwidth requirements. For example, one application may only require that a bandwidth of 10 kHz be accommodated while another application may require a bandwidth of 100 kHz. For this case, the input modulator of the sigma delta ADC would have to accommodate an input signal bandwidth of at least 100 kHz. Accommodating this 100 kHz bandwidth establishes an equivalent noise level and thereby a dynamic range for the ADC. Unfortunately, this dynamic range is less than a dynamic range that the sigma delta ADC could provide for an input signal bandwidth of only 10 kHz.
Accordingly, what is needed in the art is a way for a general purpose sigma delta ADC to provide a dynamic range commensurate with an input signal bandwidth.